Dhananjay Joshi

Dhananjay Joshi

@djay23github

Interested in ASIC Physical Design | Circuit Design | RTL Design

1
Followers
7
Following
8
Public Repos
0
Private Repos

Language Breakdown

Lines of code distribution across 8 owned repositories

41.7M Total LOC
Verilog
22,453,211 lines
53.8%
N/A
VHDL
19,015,069 lines
45.6%
N/A
SystemVerilog
102,620 lines
0.2%
N/A
Tcl
65,762 lines
0.2%
N/A
C
50,973 lines
0.1%
N/A
Other
54,699 lines
0.1%
N/A
T

T-Shaped Developer

T-shaped

Deep in Verilog with broad versatility

Verilog
VHDL
SystemVerilog
Tcl
C

Collaboration Network

Global Impact visualization

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Dhananjay Joshi
0 active collaborators

Repos

8

PRs

0

Growth

+18%

Top Collaborators

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Coding Streak

Contribution activity over the past year

2 days
48
Contributions
40
Commits
0
Pull Requests
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Followers 1
d-ragul

Ragul D

@d-ragul
Following
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kev-cam

Kevin Cameron

@kev-cam

 rswarbrick

Rupert Swarbrick

@rswarbrick

 blackmesalabs

Kevin Hubbard

@blackmesalabs

 abdelazeem201

Ahmed Abdelazeem

@abdelazeem201

 grayresearch

Jan Gray

@grayresearch
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Synced via GitHub

Top Repositories

PacketLink_SoC

PacketLink SoC is a small mixed-clock packet transport subsystem implemented in Verilog and hardened with LibreLane on the SkyWater130nm. The design bridges a UART macro and a SERDES macro through packet framing, CRC protection, asynchronous FIFOs, and status reporting logic.

0 0
Verilog
AI_Assistant_for_PPA

A very basic application which uses gemini API to suggest PPA optimizations based on design configs

0 0
Python
RTL2GDSII_Power_Management_Unit_Design

Updated version of Power Management Unit FSM Design and Verification along with the whole PD flow and analysis

0 0
Verilog
ImageProcessing_using_Vivado

This repository is for an Image Processing Algorithm in Xilinx Vivado using an outputBuffer IP

0 0
VHDL
SDRAM-Module-Design

Implementation of SDRAM in Verilog including a behavioral model and a Realistic Model

0 0
SystemVerilog
djay23github
0 0
Block_Truncation_Coding_Unit

VLSI Design Lab Final Project ( RTL2GDSII Flow using Synopsys VCS, DC, ICC2, PrimeTime and HSpice )

0 0
Verilog
Openlane_Project

Openlane Flow project (Power Management Unit FSM ) - PDK used Skywater130nm

0 0
Verilog

Open Source Impact

Contributions to external projects

0 merged PRs

No external contributions found.